A liquid crystal display (LCD) has become one of the most popular displaying devices nowadays. Thus circuits and means for driving LCD panels are one of the key techniques to be researched and developed in modern electronic industry. Give a thin-film transistor LCD (TFT-LCD) panel for example. A TFT-LCD panel generally includes a plurality of pixel units arranged in an array; and each TFT-LCD pixel unit typically includes a thin-film transistor and a LC light valve. Gates of the thin-film transistors in the same row of the array are interconnected to a common row line, which is so-called as a scan line, while their sources are connected to respective column lines, which are so-called as data lines. The row lines are driven by gate drivers/chips while source drivers/chips are used for driving column lines.
Generally speaking, a thin-film transistor, when turned on, may transmit a driving voltage provided by the source chip to a corresponding light valve so as to rotate LC molecules in the light valve, thereby adjusting light transmittance through the light valve. Accordingly, different levels of brightness and colors can be shown, depending on the driving voltages. The driving voltages of respective light valves, on the other hand, are adjusted according to the corresponding data to be displayed in order to show desired image on the display panel. Considering physical properties of LC molecules, two kinds of driving voltages may result in the same level of rotation for the LC molecules in the same light valve. The higher one is defined as a positive polarization driving voltage, while the lower one is defined as a negative polarization driving voltage. Even though the levels of the positive polarization driving voltage and the negative polarization driving voltage are different, both of them enable a pixel unit to show substantially the same gray level or color.
For avoiding damage, lengthening life span and alleviating image retention of a LCD panel, source drivers/chips alternately drives respective columns with positive polarization driving voltages and the negative polarization driving voltages. Assuming the source chip drives a specified odd output line with a positive polarization power and drives an adjacent even output line with a negative polarization power, the positive/negative polarizations will be switched in next image-updating period. That is, a negative polarization power is used for driving the odd output line and a positive polarization power is used for driving the even output line. For achieving this purpose, dot polarization inversion is required by the source chip.
Please refer to FIG. 1. An output stage 12 of a source chip 10 is biased between operational voltages VDD and VSS. For driving a specified odd output line and an adjacent even output line through a pair of odd and even output channels, respectively, two output circuits 14A and 14B are disposed in the output stage 12 of the source chip 10. A pair of data to be displayed are inputted into the output circuits 14A and 14B and then transmitted to the specified odd output line and the adjacent even output line. As illustrated in the figure, the input signal having a lower swing range, e.g. lying between VDD/2 and VSS, is inputted into the output circuit 14A to be converted into a negative polarization driving voltage and then outputted at a node Np1. On the other hand, the input signal having a higher swing range, e.g. lying between VDD and VDD/2, is inputted into the output circuit 14B to be converted into a positive polarization driving voltage and then outputted at a node Np2. The output stage 12 further includes transmission gates TRn1, TRn2, TRp1 and TRp2 controlled by two reverse-phased control signals pol and polb to implement dot polarization inversion.
When the control signal pol is at a high level while the control signal polb is at a low level, the transmission gates TRn1 and TRp1 are turned on while the transmission gates TRn2 and TRp2 are turned off. Accordingly, the negative polarization driving voltage outputted from the output circuit 14A may be transmitted to the odd output channel, and the positive polarization driving voltage outputted from the output circuit 14B may be transmitted to the even output channel. While updating the image on the display panel, the control signal pol is switched to a low level and the control signal polb is switched to a high level so that the TRn2 and TRp2 are turned on and the transmission gates TRn1 and TRp1 are turned off. Then it becomes that the negative polarization driving voltage outputted from the output circuit 14A is transmitted to the even output channel, but the positive polarization driving voltage outputted from the output circuit 14B is transmitted to the odd output channel, thereby achieving polarization inversion for driving.
The above-mentioned prior art has the following drawbacks. The conventional dot polarization inversion mechanism is implemented with a plurality of transmission gates, and each of the transmission gates includes a pair of n-channel and p-channel MOS transistors. It is apparent that the layout size is undesirably large and the integrity is unsatisfactory. In addition, when no driving voltage is to be outputted by the output circuit, the output circuit in the output stage is supposed to provide high impedance at the output channels. The high-impedance requirement possibly has an effect on the features of the output circuit, e.g. changing the zero point of the output impedance frequency response. Moreover, since the driving power in the output stage is of high voltage and high current, the life span of transistors might be adversely affected. The resistance of transistors to electrostatic discharge (ESD) is also an issue to be carefully considered, particularly for the small transistors. Therefore, a better balance between layout size and circuit properties has been being sought.